This invention relates to a semiconductor memory device using a plurality of semiconductor memory chips mounted in one system and a semiconductor memory system using a plurality of semiconductor memory devices having the same construction as described above, and more particularly to a semiconductor memory device which is desired to be operated in apparently the same manner as a one-chip semiconductor memory device by combining and mounting semiconductor memory chips and a semiconductor memory system which is formed of a plurality of semiconductor memory chips of the preceding generation and designed according to an interface exactly the same as an interface used for one chip system of the next generation so as to design a system of the next generation in advance.
In the case where a plurality of semiconductor memory chips are mounted into a single system, it is not possible that all of the input signal lines, output signal lines and input/output signal lines, for example, in the respective chips are commonly connected simply to the corresponding signal lines. This is because, if a plurality of chips are simultaneously operated, data cannot be properly read out due to a collision among their output signals. Therefore, conventionally, the semiconductor memory system having a plurality of semiconductor memory chips mounted thereon is constructed as shown in FIG. 1, for example. An input lines 12, output lines 13 and control lines 14 are commonly connected to corresponding signal pins of semiconductor memory chips 11-1, 11-2, . . . , 11-n. A chip selection controller 15 is supplied with a chip selection signal for selecting the semiconductor memory chip 11-1, 11-2, . . . , 11-n and chip selection signals (chip enable signals) CE1, CE2, . . . , CEn output from the chip selection controller 15 are respectively supplied to chip enable pins of the semiconductor memory chips 11-1, 11-2, . . . , 11-n via chip selection signal lines 16-1, 16-2, . . . , 16-n.
With the above construction, at the time of access to the chip 11-1, 11-2, . . . , 11-n, a desired chip 11-m (m=1, 2, . . . , n) is selected and set into the enable state by outputting the chip selection signal CE1, CE2, . . . , CEn from the chip selection controller 15 and non-selected chips are set into the disable state and the output terminals of the non-selected chips are set into the high impedance state. Then, the readout, programming or erasing process is effected for the selected chip 11-m and the same process is effected for another chip by selectively changing the selected chip. In this case, it is necessary for the system to recognize that a plurality of semiconductor memory chips are mounted and each of the chips is operated as an independent chip.
With this construction, since the output terminals of the non-selected chips are set in the high impedance state, common signal lines (for example, input lines 12, output lines 13, control lines 14 or the like) can be used for signals other than the chip selection signals CE1, CE2, . . . , CEn and since each chip is independently operated, the power consumption of the system can be saved.
However, with the above construction, since the chip selection controller 15 becomes necessary and the chip selection signal lines 16-1, 16-2, . . . , 16-n are required to be arranged exclusively for the chips 11-1, 11-2, . . . , 11-n, it is necessary to arrange chip selection signal lines of a number equal to the number of chips. Further, since the chips 11-1, 11-2, . . . , 11-n are independently operated, the operation for continuously reading out data from different chips cannot be basically effected. If the address input lines and data output lines are separately arranged for the respective chips, output signals can be separately derived from the respective chips by inputting common signals as the input signal in parallel, but this cannot be applied when I/O sections are multiplexed and used as bi-directional terminals. Further, continuous access to different chips can be made by using the chip selection signals CE1, CE2, . . . , CEn as highest address signals if the address input pins of the chips 11-1, 11-2, . . . , 11-n are made completely independent from one another and the I/O sections are not multiplexed, but they cannot be used in exactly the same manner if the address inputs are multiplexed.
In a semiconductor memory system used in various types of portable electronic devices, for example, in a small-sized memory card, a semiconductor memory chip 11 is connected to card terminals 21, 22, 23, 24 via input signal lines 17, output signal lines 18, control signal lines 19 and chip selection signal line 20 as shown in FIG. 2A. On the small-sized memory card, generally, a nonvolatile semiconductor memory device is mounted and an attached circuit such as a controller is not at all provided.
In order to mount a plurality of semiconductor memory chips 11-1, 11-2, . . . , 11-n on the small-sized memory card, it is necessary to connect a plurality of chip selection signal lines 20-1, 20-2, . . . , 20-n to card terminals 24-1, 24-2, . . . , 24-n as shown in FIG. 2B, and therefore, it is impossible to set the same specification (the number of card terminals, the pitch between the terminals, the arrangement thereof and the like) as a memory card having one chip contained therein. For this reason, the same memory card driver as that used for the memory card containing one chip cannot be used and the design of the potable electronic device itself must be changed.
For example, Jpn. Pat. Appln. KOKOKU Publication No. 2-760811 and Jpn. Pat. Appln. KOKAI Publication No. 7-319765 disclose a "semiconductor integrated circuit" of such a structure as to have, instead of the above-mentioned chip selection controller 15, a memory circuit for storing chip address data in a corresponding one of respective semiconductor chips 11-1, 11-2, . . . , 11-n. In the semiconductor integrated circuit disclosed in these publications', a comparison is made between an input chip address and a stored chip address data. If there is a coincidence between them, a corresponding chip is selected, but, if there occurs a non-coincidence, a chip selection is not done. By doing so, the above-mentioned chip selection controller 15 is not necessary.
If however, many more chips are mounted on a small-sized memory card, then a comparison circuit for comparing an input chip address and a stored chip address data becomes complicated, so that there occurs a greater delay time in a chip address inputting path. This causes a greater speed difference between a normal address inputting path and the chip address inputting path and, hence, a circuit design becomes difficult.
Thus, in the conventional semiconductor memory system, the design of the system including the peripheral circuit thereof and the application method must be changed in a case wherein only one semiconductor memory chip is used and a case wherein a plurality of semiconductor memory chips are mounted.
Further, in the conventional semiconductor memory device, when a plurality of semiconductor memory chips are mounted on a single system to form a semiconductor memory system having a large memory capacity, the circuit design and application method must be changed from those used in a case wherein a single semiconductor memory chip is independently used, and it becomes necessary to recognize the presence of a plurality of semiconductor memory chips and re-construct a system. Further, in order to attain exactly the same input/output relation of the system in a case wherein a single semiconductor memory chip is used and in a case wherein a plurality of semiconductor memory chips are used, it is necessary to add various signal lines and control circuits and the cost will rise.